1. Field of the Invention
The present invention relates to voltage boosting and decoder circuits, and more particularly to semiconductor clock and decoder-driver circuits for boosting word-line voltage in a random access memory.
2. Description of Prior Art
The present invention relates to a voltage boosting word-line clock circuit including a fast decoder.
Voltage boosting circuits are described in the prior art in various configurations for a variety of purposes.
U.S. Pat. No. 4,061,929 issued Dec. 6, 1977 to Asano entitled CIRCUIT FOR OBTAINING DC VOLTAGE HIGHER THAN POWER SOURCE VOLTAGE describes a voltage boosting circuit which comprises a plurality of units connected in sequence and each composed of a condenser and a plurality of MOS-FETs without any transformer or diode.
U.S. Pat. No. 4,029,973 issued June 14, 1977 to Kobayashi et al entitled VOLTAGE BOOSTER CIRCUIT USING LEVEL SHIFTER COMPOSED OF TWO COMPLEMENTARY MIS CIRCUITS discloses an improvement for a voltage booster circuit. The improvement lies in the use of MISFETs as switching means in a level converting circuit constructed in a complementary MIS semiconductor integrated circuit and therefore the voltage loss due to the conventional switching means can be prevented.
In U.S. Pat. No. 4,216,390 issued Aug. 5, 1980 to Stewart entitled LEVEL SHIFT CIRCUIT a gating means, biased to pass current only during signal transitions, transfers binary signals from an input signal source to a latch circuit when the signal source and the latch are operated at similar voltages. Following data transfer, the operating voltage across the latch is increased. The voltage levels of the latch output signals are correspondingly increased but the state to which the latch was set is maintained and there is no steady state current conduction through the gating means.
In U.S. Pat. No. 4,045,691 issued Aug. 30, 1977 to Asano, also entitled LEVEL SHIFT CIRCUIT, a level shift circuit is disclosed including an inverter connected to a first voltage supply source and supplied with an input pulse. A condenser and a directional switching element are connected in series between the output point of the inverter and one potential point of the first voltage supply source. The input of a first MOS-FET is connected to the output of the inverter while the input of a second MOS-FET is connected to a connection point between the condenser and the directional switching element. The source of the first MOS-FET is connected to a common terminal of first and second voltage supply sources while the source of the second MOS-FET is connected to the other terminal of the second voltage supply source. An output voltage is generated between a common connecting point of the the drains of the first and second MOS-FETs and one potential point of the second voltage supply source.
Circuits for generating pulsating potentials and voltage levels outside the range of, and/or of greater magnitude than, the operating potential applied to the circuits are described in U.S. Pat. No. 4,000,412 issued Dec. 28, 1976 to Rosenthal et al entitled VOLTAGE AMPLITUDE MULTIPLYING CIRCUITS. Each circuit includes first and second transistors for applying a first voltage to one plate of a capacitor and a second voltage to the other plate of the capacitor, during one time interval. During a subsequent time interval, the first and second transistors are turned off and a third transistor applies the second potential to the one plate of the capacitor. The change in the potential at the one plate of the capacitor is coupled to the other plate of the capacitor at which is produced an output potential outside the range of the first and second voltages. The potential difference between the first voltage and the output potential difference is greater in amplitude than the potential difference between the first and second voltages. The circuit may also include means alternately applying the first voltage and then the output potential to an output point for generating pulsating signals of greater amplitude than the magnitude of the applied potential. The outputs of two or more circuits may be combined to produce direct current (d.c.) levels. Also included are circuits which operate from a pulsating source of operating potential.
Other references in the general field of voltage or level boosting include the following U.S. Patents:
U.S. Pat. No. 3,999,081 by T. Nakajima entitled CLOCK-CONTROLLED GATE CIRCUIT issued Dec. 21, 1976; PA0 U.S. Pat. No. 3,982,138 by Luisi et al entitled HIGH SPEED-LOW COST, CLOCK CONTROLLED CMOS LOGIC IMPLEMENTATION issued Sept. 21, 1976; PA0 U.S. Pat. No. 3,947,829 by Y. Suzuki entitled LOGICAL CIRCUIT APPARATUS issued Mar. 30, 1976; PA0 U.S. Pat. No. 3,943,377 by Y. Suzuki entitled LOGIC CIRCUIT ARRANGEMENT EMPLOYING INSULATED GATE FIELD EFFECT TRANSISTORS issued Mar. 9, 1976; PA0 U.S. Pat. No. 3,852,625 by M. Kubo entitled SEMICONDUCTOR CIRCUIT issued Dec. 3, 1974; PA0 U.S. Pat. No. 3,801,831 by J. S. Dame entitled VOLTAGE LEVEL SHIFTING CIRCUIT issued Apr. 2, 1974. PA0 U.S. Pat. No. 4,194,130 to Moench issued Mar. 18, 1980, entitled DIGITAL PREDECODING SYSTEM; PA0 U.S. Pat. No. 4,433,257 to Kinoshita issued Feb. 21, 1984, entitled VOLTAGE SUPPLY FOR OPERATING A PLURALITY OF CHANGING TRANSISTORS IN A MANNER WHICH REDUCES MINORITY CARRIER DISRUPTION OF ADJACENT MEMORY CELLS; PA0 U.S. Pat. No. 4,156,938 to Proebsting et al issued May 29, 1979, entitled MOSFET MEMORY CHIP WITH SINGLE DECODER AND BI-LEVEL INTERCONNECT LINES; PA0 U.S. Pat. No. 4,344,005 to Stewart issued Aug. 10, 1982, entitled POWER GATED DECODING.
A variety of decoder circuits for semiconductor memories are described in the prior art.
In U.S. Pat. No. 4,309,629 issued Jan. 5, 1982 to Kamuro, entitled MOS TRANSISTOR DECODER CIRCUIT, an MOS transistor decoder circuit is disclosed including a plurality of MOS transistors, a load element, and at least one additional MOS transistor connected to the plurality of MOS transistors and the load element for selecting either of two output terminals for the plurality of MOS transistors, through which decoded output signals are developed. The two additional MOS transistors connected to the two output terminals have normal and complement bit signals, respectively.
In U.S. Pat. No. 4,264,828 issued Apr. 28, 1981 to Perlegos et al, entitled MOS STATIC DECODING CIRCUIT, a metal-oxide-semiconductor static decoding circuit for selecting an addressed line in a high density memory array, or the like, is disclosed. The circuit is laid-out along array lines where the lines have a given pitch. Three levels of decoding are employed. The highest level permits the pulling-up of a common node in the second level decoder. The third level of decoding selects one of a plurality of array lines coupled to this node. Zero threshold voltage MOS devices are employed for coupling the first and third decoders to the second decoder.
In U.S. Pat. No. 4,259,731 issued Mar. 31, 1981 to Moench, entitled QUIET ROW SELECTION CIRCUITRY, there is provided a quiet row select circuit for holding unselected word-lines or row select lines in a memory array at a predetermined voltage potential.
Transistors are used to couple each row select line to the predetermined voltage potential. The adjacent row select lines of at least one of the adjacent select lines is always coupled to the predetermined voltage when in an unselected state. A transistor is also used to couple each of the adjacent row select lines together and this transistor is enabled whenever the adjacent row select lines are nonselected so that both row select lines are coupled together to the predetermined voltage level.
In another reference of Moench, U.S. Pat. No. 4,200,917 issued Apr. 29, 1980, entitled QUIET COLUMN DECODER, a decoder is provided for semiconductor memory systems which prevents glitches from being coupled into the silicon substrate during the period of time that the sense amplifiers are sensing data on the bit sense lines. The quiet column decoder has double clock NOR gates which allows the address lines to be continuous non-multiplexed lines. The double clocked NOR gate has two transistors for precharging a first and a second node within the NOR gate. Another transistor is coupled between the second node and a voltage reference terminal to serve as an enabling device for the NOR gate. The first node of the NOR gate serves as an output for the column decoder.
In U.S. Pat. No. 4,429,374 issued Jan. 31, 1984 to Tanimura, entitled MEMORY ARRAY ADDRESSING, an address decoder for one memory axis is disclosed which comprises NAND circuits while the address decoder for the other axis comprises NOR circuits.
A semiconductor memory circuit device comprises at least first and second decoder circuits. The first decoder circuit is so constructed as to receive at least partial address signals among address signals of a plurality of bits and to provide decoded signals of the partial address signals as intermediate signals. The second decoder circuit is so constructed as to receive the intermediate signals, to thereby provide signals for selecting from among a plurality of memory circuits a memory circuit determined by the address signals of the plurality of bits.
A publication entitled "CMOS Decoder Circuit" by L. M. Terman, at page 2135 of Vol. 25, No. 4 September 1982 of the IBM Technical Disclosure Bulletin relates to improvements in CMOS decoder circuits, and particularly to a decoder circuit which does not dissipate DC power. The decoder is followed with two branches with CMOS drivers for word-lines.
In Vol. 18, No. 12, May 1976 of the IBM Technical Disclosure Bulletin, G. H. Parikh in a publication entitled "High Speed FET Decoder" at page 3955 describes a field-effect transistor decoder circuit which allows improved speed of decoding FET random-access memories, by reducing the capacitance required to be discharged in an unselected decoder. The speed is further increased by reducing the capacitance of the nodes to be discharged wherein isolation transistor devices are provided to isolate the capacitance on word-line voltage nodes to allow bootstrapping to occur if a node has not been discharged.
Other related prior art includes the following references:
The prior art listed above is representative of the state of the art prior to the present invention, and does not anticipate or make obvious the inventive features described herein.